128 lines
3.5 KiB
ArmAsm
128 lines
3.5 KiB
ArmAsm
; lenser -- Apple //e Double Hi-Res boot loader + viewer (self-contained)
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;
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; Loads 16K to main $2000-$5FFF with ordinary reads (main half at $2000, aux half
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; at $4000), then block-copies $4000-$5FFF into auxiliary $2000-$3FFF (RAMWRT on
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; only for that clean copy, never during the boot-ROM reads), then turns on DHGR.
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; ROM read at $C65C reads sector $3D into page $27 and re-enters $0801.
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;
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; assembled by apple/viewer/assemble.py via xa
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* = $0800
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.byte $01
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entry: ; $0801, re-entered after each ROM read
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lda dpage
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cmp #$60 ; loaded $2000-$5FFF (64 pages)?
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bcs done
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lda psec
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cmp #$10
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bcc readit
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jsr seeknext
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lda #$00
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sta psec
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readit:
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lda psec
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sta $3d ; desired sector
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lda curtrk
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sta $41 ; desired track (the ROM read verifies BOTH)
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lda #$00
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sta $26
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lda dpage
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sta $27
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inc psec
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inc dpage
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ldx $2b
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jmp $c65c
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done:
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; copy main $4000-$5FFF -> aux $2000-$3FFF
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lda #$00
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sta $06
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lda #$40
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sta $07 ; src = $4000
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lda #$00
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sta $08
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lda #$20
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sta $09 ; dst = $2000
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sta $c005 ; RAMWRT on (writes go to aux)
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ldx #$20 ; 32 pages
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cpl:
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ldy #$00
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cp1:
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lda ($06),y
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sta ($08),y
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iny
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bne cp1
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inc $07
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inc $09
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dex
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bne cpl
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sta $c004 ; RAMWRT off
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; turn on Double Hi-Res
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lda $c050 ; graphics
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lda $c052 ; full screen
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lda $c054 ; page 1
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lda $c057 ; hi-res
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sta $c00d ; SET80VID (write-triggered switch -- must STA)
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sta $c05e ; SETDHIRES (write-triggered)
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#include "awyt.i"
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; advance the head one track (two half-steps) with the standard phase-overlap
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; seek. energize the NEXT phase while the current one is still on (this pulls
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; the head smoothly), then release the old phase, using on/off settle delays
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; from an acceleration table indexed by step number ($0a). the final phase is
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; released before reading.
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seeknext:
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inc curtrk ; now on the next track
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lda #$00
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sta $0a ; step index for the timing table
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jsr onestep
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jsr onestep
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lda halftrk ; release final phase before the read
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and #$03
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asl
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ora $2b
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tax
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lda $c080,x
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rts
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onestep:
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lda halftrk ; energize NEXT phase (halftrk+1), old still on
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clc
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adc #$01
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and #$03
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asl
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ora $2b
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tax
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lda $c081,x
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ldx $0a
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lda ontable,x
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jsr wait
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lda halftrk ; release OLD phase (halftrk)
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and #$03
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asl
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ora $2b
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tax
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lda $c080,x
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ldx $0a
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lda offtable,x
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jsr wait
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inc halftrk
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inc $0a
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rts
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; Apple seek timing tables (head accelerates over a move, slow first step).
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ontable: .byte $13,$0a,$08,$06,$05,$04,$04,$03
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offtable: .byte $46,$1a,$10,$0c,$0a,$09,$08,$08
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wait: ; delay loop ~ proportional to A
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tay
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w1:
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ldx #$00
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w2:
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dex
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bne w2
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dey
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bne w1
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rts
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psec: .byte $01
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dpage: .byte $20
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halftrk: .byte $00
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curtrk: .byte $00
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